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ETHERNET APPLICATION EXAMPLE

Involving Marvell Alaska 88E1512
Integrated 10/100 Mbps Energy Efficient Ethernet Transceiver

Overview

Piksi Multi can provide a 10/100 Ethernet port for network connections.  This article describes how to use a Marvell Alaska 88E1512 Ethernet PHY with Piksi Multi at a hardware level to enable this interface and refers to the Piksi Multi ethernet interface reference design files available on the resource library.

In the reference design, the recommended Marvell part operates at 3V3 and connects to the Zynq-7020 AP System on a Chip (SoC) through Piksi Multi’s high density connector 1 (HDC1).  The PHY is connected to the Zynq MIO Bank 1/501 (1V8) via the Reduced Gigabit Media Independent Interface (RGMII).

The 88E1512 also requires a 25 MHz input clock. A Discera DSC1001DI1-025.0000 is used in this reference design. The RJ-45 used has status LED’s and magnetics built-in.

After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100 link speeds and full duplex.

Fig 1. Alaska 88E1512 high level application

Pin and Connection Description

Table 1. Ethernet PHY pin assignment and definitions

** PHY Reset is handled by Piksi Multi, so no need to add an external resistor.

Status LED

Status indicator LEDs are on RJ45 connector that indicate traffic and valid link state.

Table 2. RJ45 LED status

Power supply requirement when using internal regulators

Marvell Alaska 88E1512 Ethernet PHY can be supplied with a single 3V3 supply. Please choose a supply based on the below data.

Table 3. Power supply options - Integrated Switching Regulator (REG_IN)

Table 4. Current consumption REG_IN

PCB layout considerations

• The ideal Ethernet differential impedance between the MDI0±, MDI1±, MDI2±, and MDI3± traces (between MDI0+ and MDI0-, MDI1+ and MDI1-, MDI2+ and MDI2, MDI3+ and MDI3-) should be 100 Ohm. The Ethernet differential impedance between the MDI0+/ MDI0-/MDI1+/ MDI1- MDI2+/ MDI2/ MDI3+/ MDI3- trace and GND should be 50 Ohm respectively. The designer can use the trace width of MDI0+/ MDI0-/ MDI1+/ MDI1- MDI2+/MDI2/ MDI3+/ MDI3- traces to fine tune the Ethernet differential impedance value (a wider trace has a smaller impedance value).
• The crystal/oscillator clock source and the switching noises from digital signals should be kept away from the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs. Moreover, the crystal/oscillator may be sensitive to wander capacitances and noise from other signals; it is better to deploy the crystal far away from I/O ports, high frequency signal traces, magnetic, board edges, and so on.
• The MDI0±, MDI1±, MDI2±, and MDI3± differential pairs should be routed as close as possible. The trace spacing D1 between MDI0+ and MDI0- (or between MDI1+ and MDI1-, MDI2+ and MDI2-, MDI3+ and MDI3-) pair should be in 6 ~ 8 mils. The trace width should be adjusted accordingly to yield the required trace impedance.
• The spacing D2 should be larger than 200 mils. If the PCB layout is difficult to meet this requirement, the D2 spacing should be as larger as possible.
• Route the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs as straight as possible and keep them in parallel for differential pairs.
• Keep the trace length difference between MDI0+ and MDI0- (or between MDI1+ and MDI1-, MDI2+ and MDI2-, MDI3+ and MDI3-) pair within 700 mils.
• Route the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs running symmetric, equal length and close whenever possible.
• Avoid using vias on the traces of the MDI0±, MDI1±, MDI2±, and MDI3± differential pairs. If the PCB layout really needs to use vias on the differential pairs, please match the vias to keep the differential pairs balanced.
• Uncontrolled impedance runs and stubs should be kept to minimum.
• Avoid routing the signal trace with right angle, instead, the signal trace should be routed with multiple 135° angles.
• The RJ-45 is recommended to have metal shielding that connects to chassis ground to reduce EMI emission.
• The isolated side should have the chassis ground "island" placed. The MDI pairs are placed above a continuous chassis ground plane.
• Ensure that the power supply is well regulated (3.3 V DC ±5%).

References